/* Boards included:
	a2sbub
	a5lbub
	a5sbub
	a5sevk
	a7bub
	a7lbub
	coconut
	i1bub
	i1evk
	a2spi
*/

/*
#define SERIAL_STRING		Ambarella
#define SERIAL_NUMBER		1000
#define SERIAL_INCREASE_SETP	1
#define VERSION_TYPE		pri
*/
#define MAC1 dev.eth[0].mac
#define MAC2 dev.wifi[0].mac
#define MAC3 dev.usb_eth[0].mac
//wait programming time(ms): NAND use default 0
#define PROGRAM_TIMEOUT 40000

/* Sync on 2009/05/27 (a2sbub_20) */
[a2sbub]
#define ARCH_VER		2100
#define DEFAULT_DRAM_FREQ	216
#define DRAM_SIZE		0x08000000	/* 1024 Mbit */
#define DRAM_CFG_VAL		0x1000000a
#define DRAM_EXT_MODE_VAL	0x00000004

#define DRAM_MODE____108MHZ	0x00001452
#define DRAM_TIMING1_108MHZ	0x22524d26
#define DRAM_TIMING2_108MHZ	0x00000026
#define DRAM_REF_CTL_108MHZ	0x0000883b

#define DRAM_MODE____135MHZ	0x00001452
#define DRAM_TIMING1_135MHZ	0x22524d26
#define DRAM_TIMING2_135MHZ	0x00000026
#define DRAM_REF_CTL_135MHZ	0x0000883b

#define DRAM_MODE____148MHZ	0x00001452
#define DRAM_TIMING1_148MHZ	0x22524d26
#define DRAM_TIMING2_148MHZ	0x00000026
#define DRAM_REF_CTL_148MHZ	0x0000883b

#define DRAM_MODE____162MHZ	0x00001452
#define DRAM_TIMING1_162MHZ	0x22524d26
#define DRAM_TIMING2_162MHZ	0x00000026
#define DRAM_REF_CTL_162MHZ	0x0000883b

#define DRAM_MODE____189MHZ	0x00001452
#define DRAM_TIMING1_189MHZ	0x22524d26
#define DRAM_TIMING2_189MHZ	0x00000026
#define DRAM_REF_CTL_189MHZ	0x0000883b

#define DRAM_MODE____216MHZ	0x00001652
#define DRAM_TIMING1_216MHZ	0x365b663a
#define DRAM_TIMING2_216MHZ	0x0000002a
#define DRAM_REF_CTL_216MHZ	0x00008d2f

#define DRAM_MODE____243MHZ	0x00001652
#define DRAM_TIMING1_243MHZ	0x3c5b763a
#define DRAM_TIMING2_243MHZ	0x0000002c
#define DRAM_REF_CTL_243MHZ	0x00008ed3

#define RCT_DLL0_108MHZ		0x00100620
#define RCT_DLL1_108MHZ		0x00100620
#define RCT_DLL0_135MHZ		0x00100620
#define RCT_DLL1_135MHZ		0x00100620
#define RCT_DLL0_148MHZ		0x00100620
#define RCT_DLL1_148MHZ		0x00100620
#define RCT_DLL0_162MHZ		0x00100620
#define RCT_DLL1_162MHZ		0x00100620
#define RCT_DLL0_189MHZ		0x00100620
#define RCT_DLL1_189MHZ		0x00100620
#define RCT_DLL0_216MHZ		0x00100620
#define RCT_DLL1_216MHZ		0x00100620
#define RCT_DLL0_243MHZ		0x00100620
#define RCT_DLL1_243MHZ		0x00100620

#define RCT_DLL_CTRL_SEL_VAL	0x00005ef2
#define RCT_DLL_OCD_BITS_VAL	0x00010202

#define DEFAULT_GPIO1_AFSEL	0xfbffffff
#define DEFAULT_GPIO1_DIR	0xfbffffff
#define DEFAULT_GPIO1_MASK	0x04000000
#define DEFAULT_GPIO2_AFSEL	0xfffffffe
#define DEFAULT_GPIO2_DIR	0xfffffffe
#define DEFAULT_GPIO2_MASK	0x00000001

/* Sync to 2010/6/9 */
[a5lbub]
#define ARCH_VER		5500
#define DEFAULT_DRAM_FREQ	270
#define DEFAULT_CORE_FREQ	240
#define PLL_CORE_180MHZ_VAL	0x09132100
#define PLL_CORE_240MHZ_VAL	0x09133100
#define DRAM_SIZE		0x08000000	/* 1024 Mbit */
#define DRAM_CFG_VAL		0x00042354

#define DRAM_EXT_MODE0_VAL_162MHZ	0x01001563
#define DRAM_EXT_MODE1_VAL_162MHZ	0x01010002
#define DRAM_EXT_MODE2_VAL_162MHZ	0x01020000
#define DRAM_EXT_MODE3_VAL_162MHZ	0x01030000
#define DRAM_TIMING1_VAL_162MHZ		0x02649223
#define DRAM_TIMING2_VAL_162MHZ		0x00531430
#define DRAM_TIMING3_VAL_162MHZ		0x00000051
#define RCT_DLL_CTRL_SEL_VAL_162MHZ	0x00007ee7

#define DRAM_EXT_MODE0_VAL_240MHZ	0x01001863
#define DRAM_EXT_MODE1_VAL_240MHZ	0x01010002
#define DRAM_EXT_MODE2_VAL_240MHZ	0x01020000
#define DRAM_EXT_MODE3_VAL_240MHZ	0x01030000
#define DRAM_TIMING1_VAL_240MHZ		0x26b7b663
#define DRAM_TIMING2_VAL_240MHZ		0x00892259
#define DRAM_TIMING3_VAL_240MHZ		0x0000007b
#define RCT_DLL_CTRL_SEL_VAL_240MHZ	0x00007ee5

#define DRAM_EXT_MODE0_VAL_270MHZ	0x01001863
#define DRAM_EXT_MODE1_VAL_270MHZ	0x01010002
#define DRAM_EXT_MODE2_VAL_270MHZ	0x01020000
#define DRAM_EXT_MODE3_VAL_270MHZ	0x01030000
#define DRAM_TIMING1_VAL_270MHZ		0x26b7b663
#define DRAM_TIMING2_VAL_270MHZ		0x00892259
#define DRAM_TIMING3_VAL_270MHZ		0x00000086
#define RCT_DLL_CTRL_SEL_VAL_270MHZ	0x00007ee5

#define DRAM_PAD_TERM_VAL	0x00020039
#define RCT_DLL0_VAL		0x00002000
#define RCT_DLL1_VAL		0x00002000

#define DEFAULT_GPIO0_AFSEL    	0xfffdc1ff
#define DEFAULT_GPIO0_DIR	0x00000000
#define DEFAULT_GPIO0_MASK    	0x00000000
#define DEFAULT_GPIO0_DATA    	0x00000000
#define DEFAULT_GPIO1_AFSEL    	0x7f87ffff
#define DEFAULT_GPIO1_MASK    	0x00000000
#define DEFAULT_GPIO1_DIR	0x00000000
#define DEFAULT_GPIO1_DATA	0x00000000
#define DEFAULT_GPIO2_AFSEL    	0x00c3fffe
#define DEFAULT_GPIO2_DIR    	0x00000000
#define DEFAULT_GPIO2_MASK	0x00000000
#define DEFAULT_GPIO2_DATA    	0x00000000

/* Sync to 2009/8/14 */
[a5sbub]
#define ARCH_VER		5100
#define BSP_INI			"sv\a5s\bst_a5sbub_b.ini"

#define DEFAULT_GPIO0_AFSEL    	0xfffdc1ff
#define DEFAULT_GPIO0_DIR	0x00000000
#define DEFAULT_GPIO0_MASK    	0x00000000
#define DEFAULT_GPIO0_DATA    	0x00000000
#define DEFAULT_GPIO1_AFSEL    	0xffffffff
#define DEFAULT_GPIO1_MASK    	0x00000000
#define DEFAULT_GPIO1_DIR	0x00000000
#define DEFAULT_GPIO1_DATA	0x00000000
#define DEFAULT_GPIO2_AFSEL    	0xffffffff
#define DEFAULT_GPIO2_DIR    	0x00000000
#define DEFAULT_GPIO2_MASK	0x00000000
#define DEFAULT_GPIO2_DATA    	0x00000000
#define DEFAULT_GPIO3_AFSEL    	0x00000000
#define DEFAULT_GPIO3_DIR	0x00000000
#define DEFAULT_GPIO3_MASK    	0x00000000
#define DEFAULT_GPIO3_DATA    	0x00000000

/* Sync to 2009/9/29 */
[a5sevk]
#define ARCH_VER		5100
#define BSP_INI			"sv\a5s\bst_a5sbub_b.ini"

#define DEFAULT_GPIO0_AFSEL    	0x0000c07f
#define DEFAULT_GPIO0_DIR	0x00020700
#define DEFAULT_GPIO0_MASK    	0x00020700
#define DEFAULT_GPIO0_DATA    	0x40001800
#define DEFAULT_GPIO1_AFSEL    	0x00038089
#define DEFAULT_GPIO1_MASK    	0x80400006
#define DEFAULT_GPIO1_DIR	0x80400006
#define DEFAULT_GPIO1_DATA	0x00400000
#define DEFAULT_GPIO2_AFSEL    	0x0fc3fffe
#define DEFAULT_GPIO2_DIR    	0x703c0000
#define DEFAULT_GPIO2_MASK	0x703c0000
#define DEFAULT_GPIO2_DATA    	0x30000000

/* Sync to 2011/01/17 */
[a7bub]
#define ARCH_VER		7000
#define BSP_INI			"sv\a7\bst_a7bub.ini"

#define DEFAULT_GPIO0_AFSEL    	0xfffdc1ff
#define DEFAULT_GPIO0_DIR	0x00000000
#define DEFAULT_GPIO0_MASK    	0x00000000
#define DEFAULT_GPIO0_DATA    	0x00000000
#define DEFAULT_GPIO1_AFSEL    	0xffffffff
#define DEFAULT_GPIO1_MASK    	0x00000000
#define DEFAULT_GPIO1_DIR	0x00000000
#define DEFAULT_GPIO1_DATA	0x00000000
#define DEFAULT_GPIO2_AFSEL    	0xffffffff
#define DEFAULT_GPIO2_DIR    	0x00000000
#define DEFAULT_GPIO2_MASK	0x00000000
#define DEFAULT_GPIO2_DATA    	0x00000000
#define DEFAULT_GPIO3_AFSEL    	0xffffffff
#define DEFAULT_GPIO3_DIR	0x00000000
#define DEFAULT_GPIO3_MASK    	0x00000000
#define DEFAULT_GPIO3_DATA    	0x00000000
#define DEFAULT_GPIO4_AFSEL    	0xffffffff
#define DEFAULT_GPIO4_DIR	0x00000000
#define DEFAULT_GPIO4_MASK    	0x00000000
#define DEFAULT_GPIO4_DATA    	0x00000000

#define DEFAULT_GPIO0_CTRL_ENA	0x00000000
#define DEFAULT_GPIO0_CTRL_DIR	0x00000000
#define DEFAULT_GPIO1_CTRL_ENA	0x00000000
#define DEFAULT_GPIO1_CTRL_DIR	0x00000000
#define DEFAULT_GPIO2_CTRL_ENA	0x00000000
#define DEFAULT_GPIO2_CTRL_DIR	0x00000000
#define DEFAULT_GPIO3_CTRL_ENA	0x00000000
#define DEFAULT_GPIO3_CTRL_DIR	0x00000000
#define DEFAULT_GPIO4_CTRL_ENA	0x00000000
#define DEFAULT_GPIO4_CTRL_DIR	0x00000000

[a7evk]
#define ARCH_VER		7000
#define DRAM_SIZE		0x10000000
#define BSP_INI			"sv\a7\bst_a7bub.ini"

#define DEFAULT_GPIO0_AFSEL	0x0ffec7ff
#define DEFAULT_GPIO0_DIR	0x00000000
#define DEFAULT_GPIO0_MASK	0x00000000
#define DEFAULT_GPIO0_DATA	0x00000000
#define DEFAULT_GPIO1_AFSEL	0xff94008e
#define DEFAULT_GPIO1_DIR	0x000b6040
#define DEFAULT_GPIO1_MASK	0x000b6040
#define DEFAULT_GPIO1_DATA	0x00004000
#define DEFAULT_GPIO2_AFSEL	0x0fc3e7ff
#define DEFAULT_GPIO2_DIR	0x703c1800
#define DEFAULT_GPIO2_MASK	0x703c1800
#define DEFAULT_GPIO2_DATA	0x40001800
#define DEFAULT_GPIO3_AFSEL	0x00000000
#define DEFAULT_GPIO3_DIR	0x40000000
#define DEFAULT_GPIO3_MASK	0x40000000
#define DEFAULT_GPIO3_DATA	0x40000000
#define DEFAULT_GPIO4_AFSEL	0xffff0710
#define DEFAULT_GPIO4_DIR	0x0000880c
#define DEFAULT_GPIO4_MASK	0x0000880c
#define DEFAULT_GPIO4_DATA	0x00000000

/* Sync to 2011/4/27 */
[a7lbub]
#define ARCH_VER		7500
#define BSP_INI			"sv\a7l\bst_a7lbub.ini"

#define DEFAULT_GPIO0_AFSEL     0xfffdc1ff
#define DEFAULT_GPIO0_DIR       0x00000000
#define DEFAULT_GPIO0_MASK      0x00000000
#define DEFAULT_GPIO0_DATA      0x00000000
#define DEFAULT_GPIO1_AFSEL     0xffffffff
#define DEFAULT_GPIO1_MASK      0x00000000
#define DEFAULT_GPIO1_DIR       0x00000000
#define DEFAULT_GPIO1_DATA      0x00000000
#define DEFAULT_GPIO2_AFSEL     0xffffffff
#define DEFAULT_GPIO2_DIR       0x00000000
#define DEFAULT_GPIO2_MASK      0x00000000
#define DEFAULT_GPIO2_DATA      0x00000000
#define DEFAULT_GPIO3_AFSEL     0xffffffff
#define DEFAULT_GPIO3_DIR       0x00000000
#define DEFAULT_GPIO3_MASK      0x00000000
#define DEFAULT_GPIO3_DATA      0x00000000

/* Sync to 2011/4/27 */
[a7levk]
#define ARCH_VER		7500
#define DRAM_SIZE   0x10000000
#define BSP_INI			"sv\a7l\bst_a7lbub.ini"

#define DEFAULT_GPIO0_AFSEL   0xffffc7bf
#define DEFAULT_GPIO0_DIR     0x00000840
#define DEFAULT_GPIO0_MASK    0x00000000
#define DEFAULT_GPIO0_DATA    0x00000000
#define DEFAULT_GPIO1_AFSEL   0xff83dec7
#define DEFAULT_GPIO1_DIR     0x00080010
#define DEFAULT_GPIO1_MASK    0x00000000
#define DEFAULT_GPIO1_DATA    0x00000000
#define DEFAULT_GPIO2_AFSEL   0x0fffffe0
#define DEFAULT_GPIO2_DIR     0x10000003
#define DEFAULT_GPIO2_MASK    0x00000000
#define DEFAULT_GPIO2_DATA    0x00000000
#define DEFAULT_GPIO3_AFSEL   0xff0000ff
#define DEFAULT_GPIO3_DIR     0x00ef0000
#define DEFAULT_GPIO3_MASK    0x00000000
#define DEFAULT_GPIO3_DATA    0x00800000

/* Sync to 2011/4/27 */
[a7lrdb]
#define ARCH_VER		7500
#define DRAM_SIZE		0x08000000
#define BSP_INI			"sv\a7l\bst_a7lbub.ini"

#define DEFAULT_GPIO0_AFSEL    	0xfffdc1ff
#define DEFAULT_GPIO0_DIR	0x00000000
#define DEFAULT_GPIO0_MASK    	0x00000000
#define DEFAULT_GPIO0_DATA    	0x00000000
#define DEFAULT_GPIO1_AFSEL    	0xffffffff
#define DEFAULT_GPIO1_MASK    	0x00000000
#define DEFAULT_GPIO1_DIR	0x00000000
#define DEFAULT_GPIO1_DATA	0x00000000
#define DEFAULT_GPIO2_AFSEL    	0xffffffff
#define DEFAULT_GPIO2_DIR    	0x00000000
#define DEFAULT_GPIO2_MASK	0x00000000
#define DEFAULT_GPIO2_DATA    	0x00000000
#define DEFAULT_GPIO3_AFSEL    	0xffffffff
#define DEFAULT_GPIO3_DIR	0x00000000
#define DEFAULT_GPIO3_MASK    	0x00000000
#define DEFAULT_GPIO3_DATA    	0x00000000

/* Sync on 2007/10/25 */
[civet]
#define ARCH_VER		2000
#define DEFAULT_DRAM_FREQ	243
#define DRAM_SIZE		0x04000000	/* 512 Mbit */
#define DRAM_CFG_VAL		0x10000009
#define DRAM_EXT_MODE_VAL	0x00000004

#define DRAM_MODE____135MHZ	0x00001442
#define DRAM_TIMING1_135MHZ	0x1c5244a5
#define DRAM_TIMING2_135MHZ	0x00000006
#define DRAM_REF_CTL_135MHZ	0x0000883b

#define DRAM_MODE____182MHZ	0x00001442
#define DRAM_TIMING1_182MHZ	0x265254a5
#define DRAM_TIMING2_182MHZ	0x00000009
#define DRAM_REF_CTL_182MHZ	0x00008b1f

#define DRAM_MODE____189MHZ	0x00001642
#define DRAM_TIMING1_189MHZ	0x365b65b9
#define DRAM_TIMING2_189MHZ	0x0000000a
#define DRAM_REF_CTL_189MHZ	0x00008d2f

#define DRAM_MODE____216MHZ	0x00001652
#define DRAM_TIMING1_216MHZ	0x2c5b663a
#define DRAM_TIMING2_216MHZ	0x0000000a
#define DRAM_REF_CTL_216MHZ	0x00008d2f

#define DRAM_MODE____229MHZ	0x00001642
#define DRAM_TIMING1_229MHZ	0x305b65b9
#define DRAM_TIMING2_229MHZ	0x0000000b
#define DRAM_REF_CTL_229MHZ	0x00008e01

#define DRAM_MODE____243MHZ	0x00001642
#define DRAM_TIMING1_243MHZ	0x325b6db9
#define DRAM_TIMING2_243MHZ	0x0000000c
#define DRAM_REF_CTL_243MHZ	0x00008ed3

#define DRAM_MODE____256MHZ	0x00001642
#define DRAM_TIMING1_256MHZ	0x345b75b9
#define DRAM_TIMING2_256MHZ	0x0000000c
#define DRAM_REF_CTL_256MHZ	0x00008f9f

#define DRAM_MODE____270MHZ	0x00001842
#define DRAM_TIMING1_270MHZ	0x38a476c9
#define DRAM_TIMING2_270MHZ	0x0000000d
#define DRAM_REF_CTL_270MHZ	0x00009045

#define DRAM_MODE____283MHZ	0x00001842
#define DRAM_TIMING1_283MHZ	0x38a476c9
#define DRAM_TIMING2_283MHZ	0x0000000e
#define DRAM_REF_CTL_283MHZ	0x00009045

#define RCT_DLL0_135MHZ		0x000d0d78
#define RCT_DLL1_135MHZ		0x000d0d78
#define RCT_DLL0_182MHZ		0x000d0d78
#define RCT_DLL1_182MHZ		0x000d0d78
#define RCT_DLL0_189MHZ		0x000d0d78
#define RCT_DLL1_189MHZ		0x000d0d78
#define RCT_DLL0_216MHZ		0x000e0e78
#define RCT_DLL1_216MHZ		0x000e0e78
#define RCT_DLL0_230MHZ		0x000a0a78
#define RCT_DLL1_230MHZ		0x000a0a78
#define RCT_DLL0_243MHZ		0x000000c8
#define RCT_DLL1_243MHZ		0x000000c8
#define RCT_DLL0_256MHZ		0x00070778
#define RCT_DLL1_256MHZ		0x00070778
#define RCT_DLL0_270MHZ		0x00050578
#define RCT_DLL1_270MHZ		0x00050578
#define RCT_DLL0_283MHZ		0x001c1cc8
#define RCT_DLL1_283MHZ		0x001c1cc8

#define CORE_PLL_FINE_ADJUST	0x00029c0a

/* Sync to 2009/10/14 */
[coconut]
#define ARCH_VER		5100
#define BSP_INI			"sv\a5s\bst_coconut.ini"

#define DEFAULT_GPIO0_AFSEL    	0xfffdc1ff
#define DEFAULT_GPIO0_DIR	0x00000000
#define DEFAULT_GPIO0_MASK    	0x00000000
#define DEFAULT_GPIO0_DATA    	0x00000000
#define DEFAULT_GPIO1_AFSEL    	0xffffffff
#define DEFAULT_GPIO1_MASK    	0x00000000
#define DEFAULT_GPIO1_DIR	0x00000000
#define DEFAULT_GPIO1_DATA	0x00000000
#define DEFAULT_GPIO2_AFSEL    	0xffffffff
#define DEFAULT_GPIO2_DIR    	0x00000000
#define DEFAULT_GPIO2_MASK	0x00000000
#define DEFAULT_GPIO2_DATA    	0x00000000
#define DEFAULT_GPIO3_AFSEL    	0x00000000
#define DEFAULT_GPIO3_DIR	0x00000000
#define DEFAULT_GPIO3_MASK    	0x00000000
#define DEFAULT_GPIO3_DATA    	0x00000000

/* Sync to 2010/12/09 */
[i1bub]
#define ARCH_VER		7200
#define BSP_INI			"sv\i1\bst_i1bub.ini"

#define DEFAULT_GPIO0_AFSEL    	0xff7dc1ff
#define DEFAULT_GPIO0_DIR	0x00002000
#define DEFAULT_GPIO0_MASK    	0x00802000
#define DEFAULT_GPIO0_DATA    	0x00002000
#define DEFAULT_GPIO1_AFSEL    	0xffffffff
#define DEFAULT_GPIO1_MASK    	0x00000000
#define DEFAULT_GPIO1_DIR	0x00000000
#define DEFAULT_GPIO1_DATA	0x00000000
#define DEFAULT_GPIO2_AFSEL    	0xffffffff
#define DEFAULT_GPIO2_DIR    	0x00000000
#define DEFAULT_GPIO2_MASK	0x00000000
#define DEFAULT_GPIO2_DATA    	0x00000000
#define DEFAULT_GPIO3_AFSEL    	0xffffffff
#define DEFAULT_GPIO3_DIR	0x00000000
#define DEFAULT_GPIO3_MASK    	0x00000000
#define DEFAULT_GPIO3_DATA    	0x00000000
#define DEFAULT_GPIO4_AFSEL    	0xffffffff
#define DEFAULT_GPIO4_DIR	0x00000000
#define DEFAULT_GPIO4_MASK    	0x00000000
#define DEFAULT_GPIO4_DATA    	0x00000000

#define DEFAULT_GPIO0_CTRL_ENA	0x00000000
#define DEFAULT_GPIO0_CTRL_DIR	0x00000000
#define DEFAULT_GPIO1_CTRL_ENA	0x00000000
#define DEFAULT_GPIO1_CTRL_DIR	0x00000000
#define DEFAULT_GPIO2_CTRL_ENA	0x00000000
#define DEFAULT_GPIO2_CTRL_DIR	0x00000000
#define DEFAULT_GPIO3_CTRL_ENA	0x00000000
#define DEFAULT_GPIO3_CTRL_DIR	0x00000000
#define DEFAULT_GPIO4_CTRL_ENA	0x00000000
#define DEFAULT_GPIO4_CTRL_DIR	0x00000000
#define DEFAULT_GPIO5_CTRL_ENA	0x02000001
#define DEFAULT_GPIO5_CTRL_DIR	0x02000001

/* Sync to 2010/12/09 */
[i1evk]
#define ARCH_VER		7200
#define DRAM_SIZE   0x20000000
#define BSP_INI			"sv\i1\bst_i1evk.ini"

#define DEFAULT_GPIO0_AFSEL	0xff1fc2ff
#define DEFAULT_GPIO0_DIR	0x00400400
#define DEFAULT_GPIO0_MASK	0x00400400
#define DEFAULT_GPIO0_DATA	0x00000000

#define DEFAULT_GPIO1_AFSEL	0xffbca0bb
#define DEFAULT_GPIO1_DIR	0x00000a01
#define DEFAULT_GPIO1_MASK	0x00000a01
#define DEFAULT_GPIO1_DATA	0x00000001

#define DEFAULT_GPIO2_AFSEL	0xffc3ffff
#define DEFAULT_GPIO2_DIR	0x001c0000
#define DEFAULT_GPIO2_MASK	0x001c0000
#define DEFAULT_GPIO2_DATA	0x00000000

#define DEFAULT_GPIO3_AFSEL	0x80ff0000
#define DEFAULT_GPIO3_DIR	0x7f00ffff
#define DEFAULT_GPIO3_MASK	0x7f00ffff
#define DEFAULT_GPIO3_DATA	0x0e008b96

#define DEFAULT_GPIO4_AFSEL	0xc77fe3ff
#define DEFAULT_GPIO4_DIR	0x28801c00
#define DEFAULT_GPIO4_MASK	0x28801c00
#define DEFAULT_GPIO4_DATA	0x00000000

#define DEFAULT_GPIO5_AFSEL	0x13ffffff
#define DEFAULT_GPIO5_DIR	0x60000000
#define DEFAULT_GPIO5_MASK	0x60000000
#define DEFAULT_GPIO5_DATA	0x00000000


/* Default GPIO IO PAD control setting */
#define DEFAULT_GPIO0_CTRL_ENA	0x00000000
#define DEFAULT_GPIO0_CTRL_DIR	0x00000000
#define DEFAULT_GPIO1_CTRL_ENA	0x00000000
#define DEFAULT_GPIO1_CTRL_DIR	0x00000000
#define DEFAULT_GPIO2_CTRL_ENA	0x00000000
#define DEFAULT_GPIO2_CTRL_DIR	0x00000000
#define DEFAULT_GPIO3_CTRL_ENA	0x00000000
#define DEFAULT_GPIO3_CTRL_DIR	0x00000000
#define DEFAULT_GPIO4_CTRL_ENA	0x00000000
#define DEFAULT_GPIO4_CTRL_DIR	0x00000000
#define DEFAULT_GPIO5_CTRL_ENA	0x00000000
#define DEFAULT_GPIO5_CTRL_DIR	0x00000000

/* Sync to 2011/01/17 */
[a9bub]
#define ARCH_VER		9000
#define DRAM_SIZE   0x20000000
#define BSP_INI			"sv\a7s\bst_a7sbub.ini"

#define DEFAULT_GPIO0_AFSEL    	0xff7dc1ff
#define DEFAULT_GPIO0_DIR	0x00002000
#define DEFAULT_GPIO0_MASK    	0x00802000
#define DEFAULT_GPIO0_DATA    	0x00002000
#define DEFAULT_GPIO1_AFSEL    	0x7fffffff
#define DEFAULT_GPIO1_MASK    	0x00000000
#define DEFAULT_GPIO1_DIR	0x00000000
#define DEFAULT_GPIO1_DATA	0x00000000
#define DEFAULT_GPIO2_AFSEL    	0xffffffff
#define DEFAULT_GPIO2_DIR    	0x00000000
#define DEFAULT_GPIO2_MASK	0x00000000
#define DEFAULT_GPIO2_DATA    	0x00000000
#define DEFAULT_GPIO3_AFSEL    	0xffffffff
#define DEFAULT_GPIO3_DIR	0x00000000
#define DEFAULT_GPIO3_MASK    	0x00000000
#define DEFAULT_GPIO3_DATA    	0x00000000
#define DEFAULT_GPIO4_AFSEL    	0xffffffff
#define DEFAULT_GPIO4_DIR	0x00000000
#define DEFAULT_GPIO4_MASK    	0x00000000
#define DEFAULT_GPIO4_DATA    	0x00000000

/* Default GPIO IO PAD control setting */
#define DEFAULT_GPIO0_CTRL_ENA	0x00000000
#define DEFAULT_GPIO0_CTRL_DIR	0x00000000
#define DEFAULT_GPIO1_CTRL_ENA	0x00000000
#define DEFAULT_GPIO1_CTRL_DIR	0x00000000
#define DEFAULT_GPIO2_CTRL_ENA	0x00000000
#define DEFAULT_GPIO2_CTRL_DIR	0x00000000
#define DEFAULT_GPIO3_CTRL_ENA	0x00000000
#define DEFAULT_GPIO3_CTRL_DIR	0x00000000
#define DEFAULT_GPIO4_CTRL_ENA	0x00000000
#define DEFAULT_GPIO4_CTRL_DIR	0x00000000


[a2spi]
#define ARCH_VER		2100
#define DEFAULT_DRAM_FREQ	216
#define DRAM_SIZE		0x08000000	/* 1024 Mbit */
#define DRAM_CFG_VAL		0x1000000a
#define DRAM_EXT_MODE_VAL	0x00000004

#define DRAM_MODE____108MHZ	0x00001452
#define DRAM_TIMING1_108MHZ	0x22524d26
#define DRAM_TIMING2_108MHZ	0x00000026
#define DRAM_REF_CTL_108MHZ	0x0000883b

#define DRAM_MODE____135MHZ	0x00001452
#define DRAM_TIMING1_135MHZ	0x22524d26
#define DRAM_TIMING2_135MHZ	0x00000026
#define DRAM_REF_CTL_135MHZ	0x0000883b

#define DRAM_MODE____148MHZ	0x00001452
#define DRAM_TIMING1_148MHZ	0x22524d26
#define DRAM_TIMING2_148MHZ	0x00000026
#define DRAM_REF_CTL_148MHZ	0x0000883b

#define DRAM_MODE____162MHZ	0x00001452
#define DRAM_TIMING1_162MHZ	0x22524d26
#define DRAM_TIMING2_162MHZ	0x00000026
#define DRAM_REF_CTL_162MHZ	0x0000883b

#define DRAM_MODE____189MHZ	0x00001452
#define DRAM_TIMING1_189MHZ	0x22524d26
#define DRAM_TIMING2_189MHZ	0x00000026
#define DRAM_REF_CTL_189MHZ	0x0000883b

#define DRAM_MODE____216MHZ	0x00001652
#define DRAM_TIMING1_216MHZ	0x365b663a
#define DRAM_TIMING2_216MHZ	0x0000002a
#define DRAM_REF_CTL_216MHZ	0x00008d2f

#define DRAM_MODE____243MHZ	0x00001652
#define DRAM_TIMING1_243MHZ	0x3c5b763a
#define DRAM_TIMING2_243MHZ	0x0000002c
#define DRAM_REF_CTL_243MHZ	0x00008ed3

#define RCT_DLL0_108MHZ		0x00100620
#define RCT_DLL1_108MHZ		0x00100620
#define RCT_DLL0_135MHZ		0x00100620
#define RCT_DLL1_135MHZ		0x00100620
#define RCT_DLL0_148MHZ		0x00100620
#define RCT_DLL1_148MHZ		0x00100620
#define RCT_DLL0_162MHZ		0x00100620
#define RCT_DLL1_162MHZ		0x00100620
#define RCT_DLL0_189MHZ		0x00100620
#define RCT_DLL1_189MHZ		0x00100620
#define RCT_DLL0_216MHZ		0x00100620
#define RCT_DLL1_216MHZ		0x00100620
#define RCT_DLL0_243MHZ		0x00100620
#define RCT_DLL1_243MHZ		0x00100620

#define RCT_DLL_CTRL_SEL_VAL	0x00005ef2
#define RCT_DLL_OCD_BITS_VAL	0x00010202

#define DEFAULT_GPIO1_AFSEL	0xfbffffff
#define DEFAULT_GPIO1_DIR	0xfbffffff
#define DEFAULT_GPIO1_MASK	0x04000000
#define DEFAULT_GPIO2_AFSEL	0xfffffffe
#define DEFAULT_GPIO2_DIR	0xfffffffe
#define DEFAULT_GPIO2_MASK	0x00000001
#define DRAM_SIZE           0x04000000 /* 512 Mbit */
#define DRAM_CFG_VAL           0x10000009
#define DRAM_EXT_MODE_VAL 0x00000004

#define DRAM_MODE____216MHZ  0x00001632
#define DRAM_TIMING1_216MHZ    0x365b6638
#define DRAM_TIMING2_216MHZ    0x0000002a
#define DRAM_REF_CTL_216MHZ    0x00008d2d

#define RCT_DLL0_216MHZ             0x00100620
#define RCT_DLL1_216MHZ             0x00100620

#define RCT_DLL_CTRL_SEL_VAL    0x00007000
#define RCT_DLL_OCD_BITS_VAL    0x00091556